TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.12.2 EMAC Peripheral Register Descriptions
The memory maps of the EMAC are shown in Table 8-44 to Table 8-46.
Table 8-44. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS
02C8 0000
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
02C8 0004
TXCONTROL
TXTEARDOWN
-
02C8 0008
Transmit Teardown register
02C8 000F
Reserved
02C8 0010
RXIDVER
Receive Identification and Version Register
Receive Control Register
02C8 0014
RXCONTROL
RXTEARDOWN
-
02C8 0018
Receive Teardown Register
02C8 001C
Reserved
02C8 0020 - 02C8 007C
02C8 0080
-
Reserved
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACE0IVECTOR
-
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
02C8 0084
02C8 0088
02C8 008C
02C8 0090
02C8 0094
MAC End of Interrupt Vector Register
Reserved
02C8 0098 - 02C8 019C
02C8 00A0
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
-
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Reserved
02C8 00A4
02C8 00A8
02C8 00AC
02C8 00B0
02C8 00B4
02C8 00B8
02C8 00BC
02C8 00C0 - 02C8 00FC
02C8 0100
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
02C8 0104
02C8 0108
02C8 010C
02C8 0110
RXBUFFEROFFSET
02C8 0114
RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
02C8 0118 - 02C8 011C
02C8 0120
-
Reserved
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
02C8 0124
02C8 0128
02C8 012C
02C8 0130
02C8 0134
02C8 0138
02C8 013C
02C8 0140
02C8 0144
02C8 0148
02C8 014C
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Peripheral Information and Electrical Specifications
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