TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-109. Timing Requirements for Receive Data for the VLYNQ Module(1) (see Figure 6-56)
-400
-500
-600
NO.
UNIT
MIN
MAX
RTM disabled, RTM sample = 3
RTM enabled
1.75
ns
ns
ns
ns
Setup time, VLYNQ_RXD[3:0] valid before
VLYNQ_CLK high
3
4
tsu(RXDV-VCLKH)
(1)
RTM disabled, RTM sample = 3
RTM enabled
2
Hold time, VLYNQ_RXD[3:0] valid after
VLYNQ_CLK high
th(VCLKH-RXDV)
(1)
(1) The VLYNQ receive timing manager (RTM) is a serial receive logic designed to eliminate setup and hold violations that could occur in
traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see Table 6-110). When
RTM logic is disabled, the setup and hold timing from the default data flop (3) is used.
Table 6-110. RTM RX Data Flop Hold/Setup Timing
Constraints
RX Data Flop
HOLD (Y)
SETUP (X)
0
1
2
3
4
5
6
7
0.6
1.4
1.9
2
2.5
2.25
2
1.75
1.5
1.25
1
2.5
3
3.5
4
0.75
1
VLYNQ_CLK
2
Data
Data
VLYNQ_TXD[3:0]
VLYNQ_RXD[3:0]
4
3
Figure 6-56. VLYNQ Transmit/Receive Timing
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