TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.22 VLYNQ
The DM6437 VLYNQ peripheral provides a high speed serial communications interface with the following
features.
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Low Pin Count
Scalable Performance / Support
Simple Packet Based Transfer Protocol for Memory Mapped Access
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Write Request / Data Packet
Read Request Packet
Read Response Data Packet
Interrupt Request Packet
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Supports both Symmetric and Asymmetric Operation
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Tx pins on first device connect to Rx pins on second device and vice versa
Data pin widths are automatically detected after reset
Request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins
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Supports both Host/Peripheral and Peer to Peer communication
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Simple Block Code Packet Formatting (8b/10b)
In Band Flow Control
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No extra pins needed
Allows receiver to momentarily throttle back transmitter when overflow is about to occur
Uses built in special code capability of block code to seamlessly interleave flow control information
with user data
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Allows system designer to balance cost of data buffering versus performance
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Multiple outstanding transactions
Automatic packet formatting optimizations
Internal loop-back mode
6.22.1 VLYNQ Peripheral Register Description(s)
Table 6-105. VLYNQ Registers
HEX ADDRESS RANGE
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 100C
0x01E0 1010
0x01E0 1014
0x01E0 1018
0x01E0 101C
0x01E0 1020
0x01E0 1024
0x01E0 1028
0x01E0 102C
0x01E0 1030
0x01E0 1034
0x01E0 1038
ACRONYM
REGISTER NAME
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Reserved
CTRL
STAT
VLYNQ Local Control Register
VLYNQ Local Status Register
INTPRI
VLYNQ Local Interrupt Priority Vector Status/Clear Register
VLYNQ Local Unmasked Interrupt Status/Clear Register
VLYNQ Local Interrupt Pending/Set Register
INTSTATCLR
INTPENDSET
INTPTR
XAM
VLYNQ Local Interrupt Pointer Register
VLYNQ Local Transmit Address Map Register
RAMS1
RAMO1
RAMS2
RAMO2
RAMS3
RAMO3
RAMS4
VLYNQ Local Receive Address Map Size 1 Register
VLYNQ Local Receive Address Map Offset 1 Register
VLYNQ Local Receive Address Map Size 2 Register
VLYNQ Local Receive Address Map Offset 2 Register
VLYNQ Local Receive Address Map Size 3 Register
VLYNQ Local Receive Address Map Offset 3 Register
VLYNQ Local Receive Address Map Size 4 Register
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Peripheral Information and Electrical Specifications
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