TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.22.2 VLYNQ Electrical Data/Timing
Table 6-106. Timing Requirements for VLYNQ_CLK Input (see Figure 6-55)
-400
-500
-600
NO.
UNIT
MIN
MAX
1
2
3
tc(VCLK)
Cycle time, VLYNQ_CLK
10
3
ns
ns
ns
tw(VCLKH)
tw(VCLKL)
Pulse duration, VLYNQ_CLK high
Pulse duration, VLYNQ_CLK low
3
Table 6-107. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLK
Output (see Figure 6-55)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
tc(VCLK)
Cycle time, VLYNQ_CLK
10
4
ns
ns
ns
tw(VCLKH)
tw(VCLKL)
Pulse duration, VLYNQ_CLK high
Pulse duration, VLYNQ_CLK low
4
1
2
VLYNQ_CLK
3
Figure 6-55. VLYNQ_CLK Timing for VLYNQ
Table 6-108. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for
the VLYNQ Module (see Figure 6-56)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
td(VCLKH-
TXDI)
1
2
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] valid
2.25
ns
ns
td(VCLKH-
TXDV)
8.5
296
Peripheral Information and Electrical Specifications
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