TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
HCS
16
16
17
17
HAS
10
10
9
9
9
9
HCNTL[1:0]
10
10
10
9
HR/W
10
9
HHWIL
4
3
3
(A)(C)
HSTROBE
12
12
11
11
HD[15:0]
(output)
1st Half-Word
2nd Half-Word
13
13
19
18
19
18
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state
of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User’s Guide (literature number
SPRU998).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by
parametersfor HSTROBE.
Figure 6-35. HPI16 Write Timing (HAS Used)
250
Peripheral Information and Electrical Specifications
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