TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.14.2 McBSP Electrical Data/Timing
6.14.2.1 Multichannel Buffered Serial Port (McBSP) Timing
Table 6-60. Timing Requirements for McBSP(1) (see Figure 6-36)
-400
-500
-600
NO.
UNIT
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P(2)(3)
P - 1(4)
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
14
4
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
6
3
14
4
7
3
8
Hold time, DR valid after CLKR low
3
14
4
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
6
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Peripheral Information and Electrical Specifications
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