TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
HCS
16
16
17
17
HAS
10
10
10
10
9
9
9
9
HCNTL[1:0]
10
9
HR/W
10
9
HHWIL
3
4
3
HSTROBE(A)(C)
15
14
15
14
8
6
8
6
HD[15:0]
HRDY(B)
1st Halfword
13
2nd Halfword
7
19
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state
of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User's Guide
(literature number SPRU998).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by
parameters for HSTROBE.
Figure 6-33. HPI16 Read Timing (HAS Used)
248
Peripheral Information and Electrical Specifications
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