TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
HCS
HAS
HCNTL[1:0]
HR/W
1
1
1
1
2
2
2
2
2
1
1
2
3
HHWIL
(A)(C)
3
4
HSTROBE
11
11
12
12
2nd Half-Word
18
HD[15:0]
(input)
1st Half-Word
18
5
13
13
5
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User’s Guide (literature number
SPRU998).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by
parameters for HSTROBE.
Figure 6-34. HPI16 Write Timing (HAS Not Used, Tied High)
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Peripheral Information and Electrical Specifications
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