TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.13 Host-Port Interface (HPI) Peripheral
6.13.1 HPI Device-Specific Information
The DM6437 device includes a user-configurable 16-bit Host-port interface (HPI16).
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the
DM6437.
6.13.2 HPI Peripheral Register Description(s)
Table 6-55. HPI Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
01C6 7800
PID
Peripheral Identification Register
The CPU has read/write
access to the
01C6 7804
PWREMU_MGMT
HPI power and emulation management register
PWREMU_MGMT register.
01C6 7808 - 01C6 7824
01C6 7828
-
-
-
Reserved
Reserved
Reserved
01C6 782C
The Host and the CPU both
have read/write access to the
HPIC register.
01C6 7830
01C6 7834
HPIC
HPI control register
HPIA
HPI address register
(Write)
The Host has read/write
access to the HPIA registers.
The CPU has only read
(HPIAW)(1)
HPIA
HPI address register
(Read)
01C6 7838
(HPIAR)(1)
access to the HPIA registers.
01C6 780C - 01C6 7FFF
-
Reserved
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently. For more details about the HPIA registers and their
modes, see the TMS320C643x DMP Host Port Interface (HPI) User's Guide (literature number SPRU998).
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Peripheral Information and Electrical Specifications
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