TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.12.1 I2C Peripheral Register Description(s)
Table 6-52. I2C Registers
HEX ADDRESS RANGE
0x1C2 1000
0x1C2 1004
0x1C2 1008
0x1C2 100C
0x1C2 1010
0x1C2 1014
0x1C2 1018
0x1C2 101C
0x1C2 1020
0x1C2 1024
0x1C2 1028
0x1C2 102C
0x1C2 1030
0x1C2 1034
0x1C2 1038
ACRONYM
ICOAR
ICIMR
REGISTER NAME
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
I2C Clock Divider Low Register
I2C Clock Divider High Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
ICPID1
ICPID2
I2C Peripheral Identification Register 1
I2C Peripheral Identification Register 2
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Peripheral Information and Electrical Specifications
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