TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.12.2 I2C Electrical Data/Timing
6.12.2.1 Inter-Integrated Circuits (I2C) Timing
Table 6-53. Timing Requirements for I2C Timings(1) (see Figure 6-30)
-400
-500
-600
NO.
UNIT
STANDARD
MODE
FAST MODE
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
th(SCLL-SDAL)
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
0(3) 0.9(4)
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
4.7
1.3
µs
(5)
9
tr(SDA)
Rise time, SDA
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
ns
pF
(5)
(5)
(5)
10
11
12
13
14
15
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
tw(SP)
50
(5)
Cb
400
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-30. I2C Receive Timings
242
Peripheral Information and Electrical Specifications
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