TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-31. Preview Engine Register Descriptions (continued)
HEX ADDRESS RANGE
0x01C7 0880
REGISTER ACRONYM
SET_TBL_ADDRESS
SET_TBL_DATA
DESCRIPTION
Setup Table Addresses
Setup Table Data
0x01C7 0884
6.10.1.3 Resizer
The resizer module can accept input image/video data from either the preview engine or DDR2. The
output of the resizer module is sent to DDR2. The following features are supported by the resizer module.
•
•
•
•
An output width up to 1280 horizontal pixels.
Input from external DDR2.
Up to 4x upsampling (digital zoom).
Bi-cubic interpolation (4-tap horizontal, 4-tap vertical) can be implemented with the programmable filter
coefficients.
•
•
•
•
•
•
8 phases of filter coefficients.
Optional bi-linear interpolation for the chrominance components.
Up to 1/4x downsampling
4-tap horizontal and 4-tap vertical filter coefficients (with 8-phases) for 1x to 1/2x downsampling
1/2x to 1/4x downsampling, for 7-tap mode with 4-phases.
Resizing either YUV 4:2:2 packed data (16-bits) or color separate data (8-bit data within DDR) that is
contiguous.
•
•
•
Separate/independent resizing factor for the horizontal and vertical directions.
Upsampling and downsampling ratios that are available are: 256/N, with N ranging from 64 to 1024.
Programmable luminance sharpening after the horizontal resizing and before the vertical resizing step.
The Resizer register memory mapping is shown in Table 6-32.
Table 6-32. Resizer Register Descriptions
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C7 0C00
0x01C7 0C04
0x01C7 0C08
0x01C7 0C0C
0x01C7 0C10
0x01C7 0C14
0x01C7 0C18
0x01C7 0C1C
0x01C7 0C20
0x01C7 0C24
0x01C7 0C28
0x01C7 0C2C
0x01C7 0C30
0x01C7 0C34
0x01C7 0C38
0x01C7 0C3C
0x01C7 0C40
0x01C7 0C44
0x01C7 0C48
0x01C7 0C4C
PID
Peripheral Revision and Class Information
Peripheral Control Register
PCR
RSZ_CNT
OUT_SIZE
IN_START
IN_SIZE
Resizer Control Bits
Output Width and Height After Resizing
Input Starting Information
Input Width and Height Before Resizing
Input SDRAM Address
SDR_INADD
SDR_INOFF
SDR_OUTADD
SDR_OUTOFF
HFILT10
SDRAM Offset for the Input Line
Output SDRAM Address
SDRAM Offset for the Output Line
Horizontal Filter Coefficients 1 and 0
Horizontal Filter Coefficients 3 and 2
Horizontal Filter Coefficients 5 and 4
Horizontal Filter Coefficients 7 and 6
Horizontal Filter Coefficients 9 and 8
Horizontal Filter Coefficients 11 and 10
Horizontal Filter Coefficients 13 and 12
Horizontal Filter Coefficients 15 and 14
Horizontal Filter Coefficients 17 and 16
Horizontal Filter Coefficients 19 and 18
HFILT32
HFILT54
HFILT76
HFILT98
HFILT1110
HFILT1312
HFILT1514
HFILT1716
HFILT1918
218
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
