TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-27. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller(1)(2)(see Figure 6-18)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
1
tc(DDR_CLK0)
Cycle time, DDR_CLK0
6
8
ns
(1) DDR_CLK0 cycle time = 2 x PLL2 _SYSCLK1 cycle time.
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range.
1
DDR_CLK0
Figure 6-18. DDR2 Memory Controller Clock Timing
6.10 Video Processing Sub-System (VPSS) Overview
The DM6437 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input
interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video
Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital
LCD panels, HDTV video encoders, etc.
The VPSS register memory mapping is shown in Table 6-28.
Table 6-28. VPSS Register Descriptions
HEX ADDRESS RANGE
0x01C7 3400
REGISTER ACRONYM
Description
Peripheral Revision and Class Information
VPSS Control Register
PID
PCR
-
0x01C7 3404
0x01C7 3408
Reserved
0x01C7 3508
SDR_REG_EXP
-
SDRAM Non Real-Time Read Request Expand
Reserved
0x01C7 350C -
0x01C7 3FFF
6.10.1 Video Processing Front-End (VPFE)
The Video Processing Front-End (VPFE) consists of the CCD Controller (CCDC), Preview Engine,
Resizer, Hardware 3A (H3A) Statistic Generator, and Histogram blocks. Together, these modules provide
DM6437 with a powerful and flexible front-end interface. These modules are briefly described below:
•
•
The CCDC provides an interface to image sensors and digital video sources.
The Preview Engine is a parameterized hardwired image processing block which is used for converting
RAW color data from a Bayer pattern to YUV 4:2:2.
•
•
The Resizer module re-sizes the input image data to the desired display or video encoding resolution.
The H3A module provides control loops for Auto Focus (AF), Auto White Balance (AWB) and Auto
Exposure (AE).
•
The Histogram module bins input color pixels, depending on the amplitude, and provides statistics
required to implement various 3A (AE/AF/AWB) algorithms and tune the final image/video output.
The VPFE register memory mapping is shown in Table 6-29.
214
Peripheral Information and Electrical Specifications
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