TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 3-44. EMIFA/VPSS Sub-Block 0 Configuration Choice B (continued)
MAJOR
MINOR
PINMUX SELECTION FIELDS
RESULTING PERIPHERALS/PINS
CONFIG CONFIG
OPTION OPTION
PCIEN
AEM
AEAW
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[16:0]
only
8-to-12-bit
CCDC
Config Summary
No PCI
0-to-6 GP pins
1 = PCLK,
YI[7:0]
CCDCSEL = 1
-
-
HVDSEL = 0,1
-
1 = VD, HD
-
0 = GP[53:52]
-
CWENSEL = 0
0 = EM_R/W
B
B4
0
001
010
0 = EM_A21
(not used)
CFLDSEL = 0,1
1 = C_FIELD
-
-
CI10SEL = 0,1
CI32SEL = 0,1
-
-
1 = CI[1:0]
1 = CI[3:2]
0 = GP[45:44]
0 = GP[47:46]
0 =
CI54SEL = 0
CI76SEL = 0
-
-
-
-
EM_A[15:16]
0 =
EM_A[13:14]
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[18:0]
only
8-to-10-bit
CCDC
Config Summary
No PCI
0-to-4 GP pins
1 = PCLK,
YI[7:0]
CCDCSEL = 1
-
-
HVDSEL = 0,1
-
1 = VD, HD
-
0 = GP[53:52]
-
CWENSEL = 0
0 = EM_R/W
B
B5
0
001
011
0 = EM_A21
(not used)
CFLDSEL = 0,1
CI10SEL = 0,1
CI32SEL = 0
1 = C_FIELD
-
-
-
1 = CI[1:0]
-
0 = GP[45:44]
-
0 =
EM_A[17:18]
0 =
CI54SEL = 0
CI76SEL = 0
-
-
-
-
EM_A[15:16]
0 =
EM_A[13:14]
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Device Configurations
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