TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 3-47. EMIFA/VPSS Sub-Block 0 Configuration Choice E(1)
PINMUX SELECTION FIELDS
AEA
RESULTING PERIPHERALS/PINS
MAJOR
CONFIG CONFIG
OPTION OPTION
MINOR
PCIEN
AEM
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
21 GP pins
W
8-bit EMIFA
(NAND) Pinout
mode 5
Cfg Summary
No PCI
No CCDC
CCDCSEL = 0
HVDSEL = 0
CWENSEL = 0
CFLDSEL = 0
CI10SEL = 0
CI32SEL= 0
CI54SEL = 0
CI76SEL = 0
0 = GP[54, 43:36]
0 = GP[53:52]
0 = GP[35]
E1
0
101
000
0 = GP[34]
-
-
-
0 = GP[45:44]
0 = GP[47:46]
0 = GP[49:48]
0 = GP[51:50]
E
8-bit EMIFA
(NAND) Pinout
mode 5
8-to-16-bit
CCDC
Cfg Summary
No PCI
0-to-12 GP pins
CCDCSEL = 1
HVDSEL = 0,1
CWENSEL = 0,1
CFLDSEL = 0,1
CI10SEL = 0,1
CI31SEL = 0,1
CI54SEL = 0,1
CI76SEL = 0,1
1 = PCLK, YI[7:0]
1= VD, HD
1 = C_WEN
1 = C_FIELD
1 = CI[1:0]
-
0 = GP[53:52]
0 = GP[35]
0 = GP[34]
0 = GP[45:44]
0 = GP[47:46]
0 = GP[49:48]
0 = GP[51:50]
E2
0
101
000
-
-
1 = CI[3:2]
1 = CI[5:4]
1 = CI[7:6]
(1) Italics indicate mandatory settings for a given Minor Configuration option.
Submit Documentation Feedback
Device Configurations
141
TI [ TEXAS INSTRUMENTS ]
