TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 3-44. EMIFA/VPSS Sub-Block 0 Configuration Choice B(1)
MAJOR
MINOR
PINMUX SELECTION FIELDS
RESULTING PERIPHERALS/PINS
CONFIG CONFIG
OPTION OPTION
PCIEN
AEM
AEAW
OTHERS
PCI
EMIFA
VPFE
# GPIO PINS
11 GP pins
8-bit EMIFA
(Async) Pinout
mode 1 w/
Config Summary
No PCI
No CCDC
EM_A[21:0]
0 = GP[54,
43:36]
CCDCSEL = 0
-
HVDSEL = 0
CWENSEL = 0
CFLDSEL = 0
-
0 = GP[53:52]
0 = EM_R/W
0 = EM_A21
-
-
B
B1
0
001
100
0 =
CI10SEL = 0
CI32SEL = 0
CI54SEL = 0
CI76SEL = 0
-
-
-
-
-
-
EM_A[19:20]
0 =
EM_A[17:18]
0 =
EM_A[15:16]
0 =
EM_A[13:14]
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[12:0]
only
8-to-16-bit
CCDC
0-to-10 GP
pins
Config Summary
No PCI
1 = PCLK,
YI[7:0]
CCDCSEL = 1
-
-
HVDSEL = 0,1
-
1 = VD, HD
-
0 = GP[53:52]
-
B
B2
0
001
000
CWENSEL = 0
0 = EM_R/W
0 = EM_A21
(not used)
CFLDSEL = 0,1
1 = C_FIELD
-
-
CI10SEL = 0,1
CI32SEL = 0,1
CI54SEL = 0,1
CI76SEL = 0,1
-
-
-
-
1 = CI[1:0]
1 = CI[3:2]
1 = CI[5:4]
1 = CI[7:6]
0 = GP[45:44]
0 = GP[47:46]
0 = GP[49:48]
0 = GP[51:50]
8-bit EMIFA
(Async) Pinout
mode 1 w/
EM_A[14:0]
only
8-to-14-bit
CCDC
Config Summary
No PCI
0-to-8 GP pins
1 = PCLK,
YI[7:0]
CCDCSEL = 1
-
-
HVDSEL = 0,1
-
1 = VD, HD
-
0 = GP[53:52]
-
B
B3
0
001
001
CWENSEL = 0
0 = EM_R/W
0 = EM_A21
(not used)
CFLDSEL = 0,1
1 = C_FIELD
-
-
CI10SEL = 0,1
CI32SEL = 0,1
CI54SEL = 0,1
-
-
-
1 = CI[1:0]
1 = CI[3:2]
1 = CI[5:4]
0 = GP[45:44]
0 = GP[47:46]
0 = GP[49:48]
0 =
CI76SEL = 0
-
-
EM_A[13:14]
(1) Italics indicate mandatory settings for a given Minor Configuration option.
136 Device Configurations
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