TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-7
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
Bit
Field
Description
31-16 Reserved
Reserved
15
14
13
12
11
10
9
NMI7
NMI6
NMI5
NMI4
NMI3
NMI2
NMI1
NMI0
LR7
CorePac7 in NMI
CorePac6 in NMI
CorePac5 in NMI
CorePac4 in NMI
CorePac3 in NMI
CorePac2 in NMI
CorePac1 in NMI
8
CorePac0 in NMI
7
CorePac7 in local reset
CorePac6 in local reset
CorePac5 in local reset
CorePac4 in local reset
CorePac3 in local reset
CorePac2 in local reset
CorePac1 in local reset
CorePac0 in local reset
6
LR6
5
LR5
4
LR4
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 3-7
3.3.7 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The
LRESETNMI PIN Status Clear Register is shown in Figure 3-6 and described in Table 3-8
Figure 3-6
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
R, +0000 0000 0000 0000
NMI7 NMI6 NMI5 NMI4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
WC,
+0
WC,
+0
WC,
+0
WC,
+0
WC,
+0
WC, WC, WC, WC, WC, WC, WC, WC, WC, WC, WC,
+0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
82
Device Configuration
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