欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320C6678XCYP25 参数 Datasheet PDF下载

TMS320C6678XCYP25图片预览
型号: TMS320C6678XCYP25
PDF下载: 下载PDF文件 查看货源
内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 242 页 / 2088 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320C6678XCYP25的Datasheet PDF文件第80页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第81页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第82页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第83页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第85页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第86页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第87页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第88页  
TMS320C6678  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS691D—April 2013  
www.ti.com  
3.3.8 Reset Status (RESET_STAT) Register  
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the  
global device reset (GR). Software can use this information to take different device initialization steps, if desired.  
In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives  
an local reset without receiving a global reset.  
In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is  
asserted.  
The Reset Status Register is shown in Figure 3-7 and described in Table 3-9.  
Figure 3-7  
Reset Status Register (RESET_STAT)  
31  
GR  
30  
8
7
6
5
4
3
2
1
0
Reserved  
LR7  
R,+0  
LR6  
R,+0  
LR5  
R,+0  
LR4  
R,+0  
LR3  
R,+0  
LR2  
R,+0  
LR1  
R,+0  
LR0  
R,+0  
R, +1  
R, + 000 0000 0000 0000 0000 0000  
Legend: R = Read only; -n = value after reset  
Table 3-9  
Reset Status Register (RESET_STAT) Field Descriptions  
Description  
Bit  
Field  
GR  
31  
Global reset status  
0 = Device has not received a global reset.  
1 = Device received a global reset.  
30-8  
7
Reserved  
LR7  
Reserved  
CorePac7 reset status  
0 = CorePac7 has not received a local reset.  
1 = CorePac7 received a local reset.  
6
5
4
3
2
1
0
LR6  
LR5  
LR4  
LR3  
LR2  
LR1  
LR0  
CorePac6 reset status  
0 = CorePac6 has not received a local reset.  
1 = CorePac6 received a local reset.  
CorePac5 reset status  
0 = CorePac5 has not received a local reset.  
1 = CorePac5 received a local reset.  
CorePac4 reset status  
0 = CorePac4 has not received a local reset.  
1 = CorePac4 received a local reset.  
CorePac3 reset status  
0 = CorePac3 has not received a local reset.  
1 = CorePac3 received a local reset.  
CorePac2 reset status  
0 = CorePac2 has not received a local reset.  
1 = CorePac2 received a local reset.  
CorePac1 reset status  
0 = CorePac1 has not received a local reset.  
1 = CorePac1 received a local reset.  
CorePac0 reset status  
0 = CorePac0 has not received a local reset.  
1 = CorePac0 received a local reset.  
End of Table 3-9  
84  
Device Configuration  
Copyright 2013 Texas Instruments Incorporated  
 
 
 复制成功!