TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-2
Device State Control Registers (Part 4 of 4)
Address Start
0x02620340
0x02620344
0x02620348
0x0262034C
0x02620350
0x02620354
0x02620358
0x0262035C
0x02620360
0x02620364
0x02620368
0x0262036C
0x02620370
0x02620374
0x02620378
0x0262037C
0x02620380
0x02620384
0x02620388
0x026203B0
0x026203B4
0x026203B8
0x026203BC
0x026203C0
0x026203C4
0x026203C8
0x026203CC
0x026203D0
0x026203D4
0x026203D8
0x026203DC
0x026203F8
0x026203FC
0x02620400
0x02620404
End of Table 3-2
Address End
0x02620343
0x02620347
0x0262034B
0x0262034F
0x02620353
0x02620357
0x0262035B
0x0262035F
0x02620363
0x02620367
0x0262036B
0x0262036F
0x02620373
0x02620377
0x0262037B
0x0262037F
0x02620383
0x02620387
0x026203AF
0x026203B3
0x026203B7
0x026203BB
0x026203BF
0x026203C3
0x026203C7
0x026203CB
0x026203CF
0x026203D3
0x026203D7
0x026203DB
0x026203F7
0x026203FB
0x026203FF
0x02620403
0x02620467
Size
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
28B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
28B
4B
4B
4B
Field
Description
See ‘‘Related Documentation from Texas Instruments’’ on page 73
SGMII_SERDES_CFGPLL
SGMII_SERDES_CFGRX0
SGMII_SERDES_CFGTX0
SGMII_SERDES_CFGRX1
SGMII_SERDES_CFGTX1
Reserved
PCIE_SERDES_CFGPLL
Reserved
SRIO_SERDES_CFGPLL
SRIO_SERDES_CFGRX0
SRIO_SERDES_CFGTX0
SRIO_SERDES_CFGRX1
SRIO_SERDES_CFGTX1
SRIO_SERDES_CFGRX2
SRIO_SERDES_CFGTX2
SRIO_SERDES_CFGRX3
SRIO_SERDES_CFGTX3
Reserved
Reserved
Reserved
HYPERLINK_SERDES_CFGPLL
HYPERLINK_SERDES_CFGRX0
HYPERLINK_SERDES_CFGTX0
HYPERLINK_SERDES_CFGRX1
HYPERLINK_SERDES_CFGTX1
HYPERLINK_SERDES_CFGRX2
HYPERLINK_SERDES_CFGTX2
HYPERLINK_SERDES_CFGRX3
HYPERLINK_SERDES_CFGTX3
Reserved
See ‘‘Related Documentation from Texas Instruments’’ on page 73
Reserved
DEVSPEED
See section 3.3.20
Reserved
PKTDMA_PRI_ALLOC
See section 4.3 ‘‘Bus Priorities’’ on page 107
100B Reserved
78
Device Configuration
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