TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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Table 3-15
IPC Generation Registers (IPCGRH) Field Descriptions
Bit
Field
SRCSx
Description
31-4
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
IPCG
Reserved
Host interrupt generation.
Reads return 0.
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-15
3.3.15 IPC Acknowledgement Host (IPCARH) Register
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in
Table 3-16.
Figure 3-14
IPC Acknowledgement Register (IPCARH)
31
30
29
28
27
8
7
6
5
4
3
0
SRCC27 SRCC26 SRCC25 SRCC24
RW +0 RW +0 RW +0 RW +0
SRCC23 – SRCC4
SRCC3
RW +0
SRCC2
RW +0
SRCC1
RW +0
SRCC0
RW +0
Reserved
R, +0000
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-16
IPC Acknowledgement Register (IPCARH) Field Descriptions
Bit
Field
SRCCx
Description
31-4
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-16
84
Device Configuration
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