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TMS320C6672ACYP25 参数 Datasheet PDF下载

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型号: TMS320C6672ACYP25
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内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 228 页 / 2410 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320C6672  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS708C—February 2012  
www.ti.com  
Table 3-12  
NMI Generation Register (NMIGRx) Field Descriptions  
Description  
Bit  
31-1  
0
Field  
Reserved  
NMIG  
Reserved  
NMI pulse generation.  
Reads return 0  
Writes:  
0 = No effect  
1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.  
End of Table 3-12  
3.3.12 IPC Generation (IPCGRx) Registers  
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.  
The C6672 has two IPCGRx registers (IPCGR0 through IPCGR1). These registers can be used by external hosts or  
CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an  
interrupt pulse to CorePacx (0 <= x <= 1).  
These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.  
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field  
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is  
completely controlled by software. Any master that has access to BOOTCFG module space can write to these  
registers. The IPC Generation Register is shown in Figure 3-11 and described in Table 3-13.  
Figure 3-11  
IPC Generation Registers (IPCGRx)  
31  
30  
29  
28  
27  
8
7
6
5
4
3
1
0
SRCS27 SRCS26 SRCS25 SRCS24  
RW +0 RW +0 RW +0 RW +0  
SRCS23 – SRCS4  
SRCS3  
RW +0  
SRCS2  
RW +0  
SRCS1  
RW +0  
SRCS0  
RW +0  
Reserved  
R, +000  
IPCG  
RW +0  
RW +0 (per bit field)  
Legend: R = Read only; RW = Read/Write; -n = value after reset  
Table 3-13  
IPC Generation Registers (IPCGRx) Field Descriptions  
Bit  
Field  
SRCSx  
Description  
31-4  
Interrupt source indication.  
Reads return current value of internal register bit.  
Writes:  
0 = No effect  
1 = Sets both SRCSx and the corresponding SRCCx.  
3-1  
0
Reserved  
IPCG  
Reserved  
Inter-DSP interrupt generation.  
Reads return 0.  
Writes:  
0 = No effect  
1 = Creates an Inter-DSP interrupt.  
End of Table 3-13  
82  
Device Configuration  
Copyright 2012 Texas Instruments Incorporated  
 
 
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