TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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3.3.7 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.
•
In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.
•
In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is
asserted.
The Reset Status Register is shown in Figure 3-6 and described in Table 3-8.
Figure 3-6
Reset Status Register (RESET_STAT)
31
GR
30
2
1
0
Reserved
R, + 000 0000 0000 0000 0000 0000
LR1
R,+0
LR0
R,+0
R, +1
Legend: R = Read only; -n = value after reset
Table 3-8
Reset Status Register (RESET_STAT) Field Descriptions
Description
Bit
Field
GR
31
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
30-2
1
Reserved
LR1
Reserved.
CorePac1 reset status
0 = CorePac1 has not received a local reset.
1 = CorePac1 received a local reset.
0
LR0
CorePac0 reset status
0 = CorePac0 has not received a local reset.
1 = CorePac0 received a local reset.
End of Table 3-8
3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in Figure 3-7 and described in Table 3-9.
Figure 3-7
Reset Status Clear Register (RESET_STAT_CLR)
31
GR
30
2
1
0
Reserved
LR1
LR0
RW, +0
R, + 000 0000 0000 0000 0000 0000
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Copyright 2012 Texas Instruments Incorporated
Device Configuration 79
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