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TMS320C6672ACYP25 参数 Datasheet PDF下载

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型号: TMS320C6672ACYP25
PDF下载: 下载PDF文件 查看货源
内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 228 页 / 2410 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320C6672  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS708C—February 2012  
www.ti.com  
Table 7-52  
MPU0 Registers (Part 2 of 2)  
Offset  
294h  
298h  
2A0h  
2A4h  
2A8h  
2B0h  
2B4h  
2B8h  
2C0h  
2C4h  
2C8h  
2D0h  
2D4h  
2Dh  
Name  
Description  
PROG9_MPEAR  
PROG9_MPPA  
PROG10_MPSAR  
PROG10_MPEAR  
PROG10_MPPA  
PROG11_MPSAR  
PROG11_MPEAR  
PROG11_MPPA  
PROG12_MPSAR  
PROG12_MPEAR  
PROG12_MPPA  
PROG13_MPSAR  
PROG13_MPEAR  
PROG13_MPPA  
PROG14_MPSAR  
PROG14_MPEAR  
PROG14_MPPA  
PROG15_MPSAR  
PROG15_MPEAR  
PROG15_MPPA  
FLTADDRR  
Programmable range 9, end address  
Programmable range 9, memory page protection attributes  
Programmable range 10, start address  
Programmable range 10, end address  
Programmable range 10, memory page protection attributes  
Programmable range 11, start address  
Programmable range 11, end address  
Programmable range 11, memory page protection attributes  
Programmable range 12, start address  
Programmable range 12, end address  
Programmable range 12, memory page protection attributes  
Programmable range 13, start address  
Programmable range 13, end address  
Programmable range 13, memory page protection attributes  
Programmable range 14, start address  
Programmable range 14, end address  
Programmable range 14, memory page protection attributes  
Programmable range 15, start address  
Programmable range 15, end address  
Programmable range 15, memory page protection attributes  
Fault address  
2E0h  
2E4h  
2E8h  
2F0h  
2F4h  
2F8h  
300h  
304h  
308h  
FLTSTAT  
Fault status  
FLTCLR  
Fault clear  
End of Table 7-52  
Table 7-53  
MPU1 Registers (Part 1 of 2)  
Offset  
0h  
Name  
Description  
REVID  
Revision ID  
4h  
CONFIG  
Configuration  
10h  
IRAWSTAT  
IENSTAT  
Interrupt raw status/set  
14h  
Interrupt enable status/clear  
18h  
IENSET  
Interrupt enable  
1Ch  
IENCLR  
Interrupt enable clear  
20h  
EOI  
End of interrupt  
200h  
204h  
208h  
210h  
214h  
218h  
220h  
224h  
228h  
PROG0_MPSAR  
PROG0_MPEAR  
PROG0_MPPA  
PROG1_MPSAR  
PROG1_MPEAR  
PROG1_MPPA  
PROG2_MPSAR  
PROG2_MPEAR  
PROG2_MPPA  
Programmable range 0, start address  
Programmable range 0, end address  
Programmable range 0, memory page protection attributes  
Programmable range 1, start address  
Programmable range 1, end address  
Programmable range 1, memory page protection attributes  
Programmable range 2, start address  
Programmable range 2, end address  
Programmable range 2, memory page protection attributes  
182  
Peripheral Information and Electrical Specifications  
Copyright 2012 Texas Instruments Incorporated  
 
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