TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-50
Privilege ID Settings (Part 2 of 2)
Privilege ID Master
Privilege Level
Security Level
Access Type
9
SRIO_PKTDMA/SRIO_M
User/Driven by SRIO block, User mode and supervisor mode is
determined on a per-transaction basis. Only the transaction with
source ID matching the value in the SupervisorID register is granted
supervisor mode.
Non-secure
DMA
10
11
12
13
14
15
QM_PKTDMA/QM_second User
Non-secure
Non-secure
DMA
DMA
PCIe
Supervisor
Driven by debug_SS
Supervisor
Supervisor
User
DAP
Driven by debug_SS DMA
HyperLink
HyperLink
TSIP0/1
Non-secure
Non-secure
Non-secure
DMA
DMA
DMA
End of Table 7-50
Table 7-51 shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine
allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters,
master IDs are unique to each master.
Table 7-51
Master ID Settings (Part 1 of 2) (1)
Master ID
Master
0
CorePac0
1
CorePac1
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
CorePac0_CFG
CorePac1_CFG
Reserved
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Reserved
Reserved
Reserved
Reserved
Reserved
EDMA0_TC0 read
EDMA0_TC0 write
EDMA0_TC1 read
EDMA0_TC1 write
EDMA1_TC0 read
EDMA1_TC0 write
EDMA1_TC1 read
EDMA1_TC1 write
EDMA1_TC2 read
EDMA1_TC2 write
EDMA1_TC3 read
EDMA1_TC3 write
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 179
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