TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
7.10.2 MPU Programmable Range Registers
7.10.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The programmable address start register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also
writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines
the width of the address field in MPSAR and MPEAR.
Figure 7-32
Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-57
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
Bit
Field
Description
31 – 10
9 – 0
START_ADDR
Reserved
Start address for range n.
Reserved and these bits always read as 0.
End of Table 7-57
Table 7-58
Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
Register
MPU0
MPU1
0x3400_0000
0x3402_0000
0x3406_0000
0x3406_8000
0x340B_8000
N/A
MPU2
MPU3
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
PROG14_MPSAR
PROG15_MPSAR
End of Table 7-58
0x01D0_0000
0x01F0_0000
0x0200_0000
0x01E0_0000
0x021C_0000
0x021F_0000
0x0220_0000
0x0231_0000
0x0232_0000
0x0233_0000
0x0235_0000
0x0240_0000
0x0250_0000
0x0253_0000
0x0260_0000
0x0262_0000
0x02A0_0000
0x02A2_0000
0x02A4_0000
0x02A6_0000
0x02A6_8000
0x02A6_9000
0x02A6_A000
0x02A6_B000
0x02A6_C000
0x02A6_E000
0x02A8_0000
0x02A9_0000
0x02AA_0000
0x02AA_8000
0x02AB_0000
0x02AB_8000
0x0264_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
186
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
