TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
7.10 Memory Protection Unit (MPU)
The C6672 supports four MPUs:
•
One MPU is used to protect main CORE/3 CFG SCR (CFG space of all slave devices on the SCR is protected
by the MPU).
•
•
Two MPUs are used for QM_SS (one for DATA PORT port and another is for CFG PORT port).
One MPU is used for Semaphore.
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and
details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 69.
The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 7-48
MPU Default Configuration
MPU0
MPU1
MPU2
MPU3
Setting
Main CFG SCR
(QM_SS DATA PORT)
(QM_SS CFG PORT)
Semaphore
Default permission
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Number of allowed IDs supported
Number of programmable ranges supported
Compare width
16
16
16
16
16
5
16
1
1KB granularity
1KB granularity
1KB granularity
1KB granularity
End of Table 7-48
Table 7-49
MPU Memory Regions
Memory Protection
Main CFG SCR
Start Address
0x01D00000
0x34000000
0x02A00000
0x02640000
End Address
0x026203FF
0x340BFFFF
0x02ABFFFF
0x026407FF
MPU0
MPU1
MPU2
MPU3
QM_SS DATA PORT
QM_SS CFG PORT
Semaphore
Table 7-50 shows the privilege ID of each CORE and every mastering peripheral. Table 7-50 also shows the privilege
level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read
or write) of each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 7-50
Privilege ID Settings (Part 1 of 2)
Privilege ID Master
Privilege Level
Security Level
SW dependant
SW dependant
Access Type
DMA
0
1
2
3
4
5
6
7
8
CorePac0
CorePac1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SW dependant, driven by MSMC
SW dependant, driven by MSMC
DMA
Network Coprocessor
Packet DMA
User
Non-secure
DMA
178
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
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