TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-45
IPC Generation Registers (IPCGRx) (Part 2 of 2)
Address Start
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202BC
End of Table 7-45
Address End
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202BB
0x026202BF
Size
4B
Register Name
IPCGRH
Description
IPC Generation Register for Host
4B
IPCAR0
IPC Acknowledgement Register for CorePac 0
4B
IPCAR1
IPC Acknowledgement Register for CorePac 1
4B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCARH
Reserved
4B
Reserved
4B
Reserved
4B
Reserved
4B
Reserved
4B
Reserved
28B
4B
Reserved
IPC Acknowledgement Register for Host
7.9.4 NMI and LRESET
Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured
to select between the CorePacs available as shown in Table 7-46.
Table 7-46
LRESET and NMI Decoding (Part 1 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
XXXX
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
0000
0001
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No local reset or NMI assertion.
Assert local reset to CorePac 0
Assert local reset to CorePac 1
Reserved
Reserved
De-assert local reset & NMI to CorePac 0
De-assert local reset & NMI to CorePac 1
Reserved
De-assert local reset & NMI to all CorePacs
Assert NMI to CorePac 0
Assert NMI to CorePac 1
176
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
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