TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-46
LRESET and NMI Decoding (Part 2 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
0010
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0011
0100
Reserved
0101
0110
0111
1xxx
Assert NMI to all CorePacs
End of Table 7-46
7.9.5 External Interrupts Electrical Data/Timing
Table 7-47
NMI and Local Reset Timing Requirements (1)
(see Figure 7-30)
No.
Min
12*P
12*P
12*P
12*P
12*P
12*P
12*P
Max Unit
1
1
1
2
2
2
3
tsu(LRESET-LRESETNMIENL)
Setup Time - LRESET valid before LRESETNMIEN low
Setup Time - NMI valid before LRESETNMIEN low
Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
Hold Time - LRESET valid after LRESETNMIEN high
Hold Time - NMI valid after LRESETNMIEN high
Hold Time - CORESEL[2:0] valid after LRESETNMIEN high
Pulse Width - LRESETNMIEN low width
ns
ns
ns
ns
ns
ns
ns
tsu(NMI-LRESETNMIENL)
tsu(CORESELn-LRESETNMIENL)
th(LRESETNMIENL-LRESET)
th(LRESETNMIENL-NMI)
th(LRESETNMIENL-CORESELn)
tw(LRESETNMIEN)
End of Table 7-47
1 P = 1/SYSCLK1 clock frequency in ns.
Figure 7-30
NMI and Local Reset Timing
1
2
CORESEL[3:0]/
LRESET/
NMI
3
LRESETNMIEN
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 177