TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-44
CIC3 Register
Address Offset
0x420
Register Mnemonic
Register Name
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Int Enable Register 0
0x424
CH_MAP_REG9
0x428
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
ENABLE_HINT_REG0
ENABLE_HINT_REG1
0x42c
0x430
0x434
0x438
0x43c
0x800
0x804
0x808
0x80c
0x810
0x814
0x818
0x81c
0x820
0x824
0x1500
0x1504
End of Table 7-44
Host Int Enable Register 1
7.9.3 Inter-Processor Register Map
Table 7-45
IPC Generation Registers (IPCGRx) (Part 1 of 2)
Address Start
0x02620200
0x02620204
0x02620208
0x0262020C
0x02620210
0x02620214
0x02620218
0x0262021C
0x02620220
0x02620240
0x02620244
0x02620248
0x0262024C
0x02620250
0x02620254
0x02620258
0x0262025C
0x02620260
Address End
0x02620203
0x02620207
0x0262020B
0x0262020F
0x02620213
0x02620217
0x0262021B
0x0262021F
0x0262023F
0x02620243
0x02620247
0x0262024B
0x0262024F
0x02620253
0x02620257
0x0262025B
0x0262025F
0x0262027B
Size
4B
4B
4B
4B
4B
4B
4B
4B
32B
4B
4B
4B
4B
4B
4B
4B
4B
28B
Register Name
NMIGR0
Description
NMI Event Generation Register for CorePac0
NMIGR1
NMI Event Generation Register for CorePac 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCGR0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPC Generation Register for CorePac 0
IPCGR1
IPC Generation Register for CorePac 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 175
TI [ TEXAS INSTRUMENTS ]
