TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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Table 7-38
TMS320C6672 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)
Event Number
Interrupt Event
Description
89
GPINT15
Local GPIO interrupt
90
GPINTn (9)
Local GPIO interrupt
91
IPC_LOCAL
Inter DSP interrupt from IPCGRn
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Dropped CPU interrupt event
Invalid IDMA parameters
92
CIC0_OUT(4+8*n)
CIC0_OUT(5+8*n)
CIC0_OUT(6+8*n)
CIC0_OUT(7+8*n)
INTERR
93
94
95
96
97
EMC_IDMAERR
Reserved
98
99
Reserved
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
End of Table 7-38
EFIINTA
EFI Interrupt from side A
EFI Interrupt from side B
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
VbusM error event
EFIINTB
CIC0_OUT0
CIC0_OUT1
CIC0_OUT8
CIC0_OUT9
CIC0_OUT16
CIC0_OUT17
CIC0_OUT24
CIC0_OUT25
MDMAERREVT
Reserved
EDMA3CC0_EDMACC_AETEVT
PMC_ED
EDMA3CC0 AET event
Single bit error detected during DMA read
EDMA3CC1 AET Event
EDMA3CC1_EDMACC_AETEVT
EDMA3CC2_EDMACC_AETEVT
UMC_ED1
EDMA3CC2 AET Event
Corrected bit error detected
UMC_ED2
Uncorrected bit error detected
PDC_INT
Power down sleep interrupt
SYS_CMPA
SYS CPU memory protection fault event
PMC CPU memory protection fault event
PMC DMA memory protection fault event
DMC CPU memory protection fault event
DMC DMA memory protection fault event
UMC CPU memory protection fault event
UMC DMA memory protection fault event
EMC CPU memory protection fault event
EMC bus error interrupt
PMC_CMPA
PMC_DMPA
DMC_CMPA
DMC_DMPA
UMC_CMPA
UMC_DMPA
EMC_CMPA
EMC_BUSERR
1 CorePac[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn
2 CorePac[n] will receive MSMC_mpf_errorn.CIC
3 CorePac[n] will receive SEMINTn and SEMERRn.
4 CorePac[n] will receive PCIEXpress_MSI_INTn.
5 CorePac[n] will receive TSIPx_xxx[n]
6 CorePac[n] will receive INTDST(n+16)
160
Peripheral Information and Electrical Specifications
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