TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-37
EDMA3CC2 Events for C6672 (Part 2 of 2)
Event Number
Event
Event Description
34
TINT8L
Timer interrupt low
35
TINT8H
Timer interrupt high
36
TINT9L
Timer interrupt low
37
TINT9H
Timer interrupt high
38
CIC2_OUT48
CIC2_OUT49
URXEVT
Interrupt Controller output
Interrupt Controller output
UART receive event
39
40
41
UTXEVT
UART transmit event
42
CIC2_OUT22
CIC2_OUT23
CIC2_OUT24
CIC2_OUT25
CIC2_OUT26
CIC2_OUT27
CIC2_OUT28
CIC2_OUT29
CIC2_OUT30
CIC2_OUT31
CIC2_OUT32
CIC2_OUT33
CIC2_OUT34
CIC2_OUT35
CIC2_OUT36
CIC2_OUT37
CIC2_OUT38
CIC2_OUT39
CIC2_OUT40
CIC2_OUT41
CIC2_OUT42
CIC2_OUT43
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
End of Table 7-37
7.9 Interrupts
7.9.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6672 device are configured through the C66x CorePac Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through chip interrupt controller (CIC) blocks. This is clocked using CPU/6.
156
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
