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TMS320C6672ACYP25 参数 Datasheet PDF下载

TMS320C6672ACYP25图片预览
型号: TMS320C6672ACYP25
PDF下载: 下载PDF文件 查看货源
内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 228 页 / 2410 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320C6672  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS708C—February 2012  
www.ti.com  
Table 7-39  
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 4)  
Input Event# on CIC  
System Interrupt  
EDMA3CC0 CCINT3  
EDMA3CC0 CCINT4  
EDMA3CC0 CCINT5  
EDMA3CC0 CCINT6  
EDMA3CC0 CCINT7  
Reserved  
Description  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
81  
82  
84  
EDMA3CC0 individual completion interrupt  
EDMA3CC0 individual completion interrupt  
EDMA3CC0 individual completion interrupt  
EDMA3CC0 individual completion interrupt  
EDMA3CC0 individual completion interrupt  
QM_INT_PASS_TXQ_PEND_12  
PCIEXpress_ERR_INT  
PCIEXpress_PM_INT  
PCIEXpress_Legacy_INTA  
PCIEXpress_Legacy_INTB  
PCIEXpress_Legacy_INTC  
PCIEXpress_Legacy_INTD  
SPIINT0  
Queue manager pend event  
Protocol error interrupt  
Power management interrupt  
Legacy interrupt mode  
Legacy interrupt mode  
Legacy interrupt mode  
Legacy interrupt mode  
SPI interrupt0  
SPIINT1  
SPI interrupt1  
SPIXEVT  
Transmit event  
SPIREVT  
Receive event  
I2C interrupt  
I2C receive event  
I2C transmit event  
I2CINT  
I2CREVT  
I2CXEVT  
Reserved  
Reserved  
TETBHFULLINT  
TETB is half full  
TETBFULLINT  
TETB is full  
TETBACQINT  
Acquisition has been completed  
Overflow condition occur  
TETBOVFLINT  
TETBUNFLINT  
Underflow condition occur  
MDIO_LINK_INTR0  
MDIO_LINK_INTR1  
MDIO_USER_INTR0  
MDIO_USER_INTR1  
MISC_INTR  
Network coprocessor MDIO interrupt  
Network coprocessor MDIO interrupt  
Network coprocessor MDIO interrupt  
Network coprocessor MDIO interrupt  
Network coprocessor MISC interrupt  
Tracer sliding time window interrupt for individual core  
Tracer sliding time window interrupt for individual core  
TRACER_CORE_0_INTD  
TRACER_CORE_1_INTD  
Reserved  
Reserved  
TRACER_DDR_INTD  
TRACER_MSMC_0_INTD  
TRACER_MSMC_1_INTD  
TRACER_MSMC_2_INTD  
TRACER_MSMC_3_INTD  
TRACER_CFG_INTD  
TRACER_QM_SS_CFG_INTD  
TRACER_QM_SS_DMA_INTD  
Tracer sliding time window interrupt for DDR3 EMIF1  
Tracer sliding time window interrupt for MSMC SRAM bank0  
Tracer sliding time window interrupt for MSMC SRAM bank1  
Tracer sliding time window interrupt for MSMC SRAM bank2  
Tracer sliding time window interrupt for MSMC SRAM bank3  
Tracer sliding time window interrupt for CFG0 SCR  
Tracer sliding time window interrupt for QM_SS CFG  
Tracer sliding time window interrupt for QM_SS slave  
162  
Peripheral Information and Electrical Specifications  
Copyright 2012 Texas Instruments Incorporated  
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