TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-30
PASS PLL Control Register 0 Field Descriptions
Bit
Field
Description
31-24
BWADJ[7:0]
BYPASS
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM = 15, then BWADJ = 7
23
Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
22-19
18-6
5-0
Reserved
PLLM
Reserved
A 13-bit bus that selects the values for the multiplication factor
A 6-bit bus that selects the values for the reference divider
PLLD
End of Table 7-30
Figure 7-27
PASS PLL Control Register 1 (PASSPLLCTL1)
31
15
14
13
7
6
5
4
3
0
Reserved
RW-00000000000000000
Legend: RW = Read/Write; -n = value after reset
PLLRST
RW-0
Reserved
ENSAT
RW-0
Reserved
R-0
BWADJ[11:8]
RW-0000
RW-0000000
Table 7-31
PASS PLL Control Register 1 Field Descriptions
Description
Bit
Field
Reserved
31-15
14
Reserved
PLLRST
PLL reset bit.
0 = PLL reset is released.
1 = PLL reset is asserted.
13-7
6
Reserved
ENSAT
Reserved
Must be set to 1 for proper operation of the PLL
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM=15, then BWADJ=7
End of Table 7-31
7.7.2 PASS PLL Device-Specific Information
As shown in Figure 7-25, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Network
Coprocessor. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS
PLL are affected as described in Section 7.4 ‘‘Reset Controller’’ on page 125. The PASS PLL is unlocked only during
the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of
the other resets.
7.7.3 PASS PLL Initialization Sequence
The Main PLL and PLL Controller must always be initialized prior to initializing the PASS PLL. The sequence shown
below must be followed to initialize the PASS PLL.
1. In PASSPLLCTL1, write ENSAT = 1 (for optimal PLL operation)
2. In PASSPLLCTL0, write BYPASS = 1 (set the PLL in Bypass)
3. In PASSPLLCTL1, write PLLRST = 1 (PLL is reset)
4. Program PLLM and PLLD in PASSPLLCTL0 register
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 149
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