TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-29
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements (Part 2 of 2)
(see Figure 7-24 and Figure 7-20)
No.
Min
Max Unit
0.55*tc(DDRCLKN)
3
2
2
3
4
4
4
4
5
5
tw(DDRCLKN)
tw(DDRCLKN)
tw(DDRCLKP)
tw(DDRCLKP)
Pulse width _ DDRCLKN high
Pulse width _ DDRCLKN low
Pulse width _ DDRCLKP high
Pulse width _ DDRCLKP low
0.45*tc(DDRCLKN)
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
0.55*tc(DDRCLKP)
0.55*tc(DDRCLKP)
350
0.45*tc(DDRCLKP)
0.45*tc(DDRCLKP)
tr(DDRCLKN_250mv) Transition time _ DDRCLKN rise time (250 mV)
tf(DDRCLKN_250mv) Transition time _ DDRCLKN fall time (250 mV)
tr(DDRCLKP_250mv) Transition time _ DDRCLKP rise time (250 mV)
tf(DDRCLKP_250mv) Transition time _ DDRCLKP fall time (250 mV)
50
50
50
50
350
350
350
tj(DDRCLKN)
tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKN
Jitter, peak_to_peak _ periodic DDRCLKP
0.025*tc(DDRCLKN)
0.025*tc(DDRCLKP)
End of Table 7-29
Figure 7-24
DDR3 PLL DDRCLK Timing
1
2
3
5
DDRCLKN
DDRCLKP
4
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Peripheral Information and Electrical Specifications 147
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