TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
In the context of this document, EDMA3TCx associated with EDMA3CCy, and is referred to as EDMA3CCy TCx.
Each of the transfer controllers has a direct connection to the switch fabric. Section 4.2 ‘‘Switch Fabric Connections’’
lists the peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are
to be used for the remaining traffic.
Each EDMA3 Channel Controller includes the following features:
•
Fully orthogonal transfer description
–
3 transfer dimensions:
›
›
›
Array (multiple bytes)
Frame (multiple arrays)
Block (multiple frames)
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–
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
•
•
Flexible transfer definition:
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–
Increment or FIFO transfer addressing modes
Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
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Chaining allows multiple transfers to execute with one event
128 PaRAM entries for EDMA3CC0, 512 each for EDMA3CC1 and EDMA3CC2
–
–
Used to define transfer context for channels
Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
•
•
16 DMA channels for EDMA3CC0, 64 each for EDMA3CC1 and EDMA3CC2
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Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
8 Quick DMA (QDMA) channels per EDMA 3 Channel Controller
–
–
Used for software-driven transfers
Triggered upon writing to a single PaRAM set entry
•
2 transfer controllers and 2 event queues with programmable system-level priority for EDMA3CC0, 4 transfer
controllers and 4 event queues with programmable system-level priority per channel controller for
EDMA3CC1 and EDMA3CC2
•
•
Interrupt generation for transfer completion and error conditions
Debug visibility
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–
Queue watermarking/threshold allows detection of maximum usage of event queues
Error and status recording to facilitate debug
7.8.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode must be used.
On the C6672 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder
Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not
supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all
peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct
Memory Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 69.
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 151
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