TMP435
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SBOS495A –MARCH 2010–REVISED APRIL 2010
1
9
1
9
SCL
SDA
1
0
0
1
1
0
0(1)
R/W
P7
P6
P5
P4
P3
P2
P1
P0
Start By
Master
ACK By
ACK By
TMP435
TMP435
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
SDA
1
0
0(1)
1
0
0
1
R/W
D7
D6
D5
D4 D3
D2
D1
D0
(Continued)
Start By
Master
ACK By
From
TMP435
ACK By
Master
TMP435
Frame 3 Two-Wire Slave Address Byte
Frame 4 Data Byte 1 Read Register
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4
D3
D2
D1
D0
(Continued)
From
NACK By Stop By
Master(2)
Master
TMP435
Frame 5 Data Byte 2 Read Register
NOTES: (1) Slave address 1001100 (TMP435) shown. See Ordering Information table for more details.
(2) Master should leave SDA high to terminate a two-byte read operation.
Figure 18. Two-Wire Timing Diagram for Two-Byte Read Format
ALERT
1
9
1
9
SCL
SDA
0(1)
Status
0
0
0
1
1
0
0
R/W
1
0
0
1
1
0
Start By
Master
ACK By
From
TMP435
NACK By Stop By
Master Master
TMP435
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address Byte
NOTE (1): Slave address 1001100 (TMP435) shown. See Ordering Information table for more details.
Figure 19. Timing Diagram for SMBus ALERT
Copyright © 2010, Texas Instruments Incorporated
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