TMP435
SBOS495A –MARCH 2010–REVISED APRIL 2010
www.ti.com
Bus Overview
Two-Wire Interface Slave Device Addresses
The TMP435 is SMBus interface-compatible. In
SMBus protocol, the device that initiates the transfer
is called a master, and the devices controlled by the
master are slaves. The bus must be controlled by a
master device that generates the serial clock (SCL),
controls the bus access, and generates the START
and STOP conditions.
The TMP435 supports nine slave device addresses
and is available in two different fixed serial interface
addresses.
The A1 and A0 pins, as summarized in Table 14), set
the slave device address for the TMP435.
Table 14. Two-Wire Addresses
To address a specific device, a START condition is
initiated. START is indicated by pulling the data line
(SDA) from a high to low logic level while SCL is
high. All slaves on the bus shift in the slave address
byte, with the last bit indicating whether a read or
write operation is intended. During the ninth clock
pulse, the slave being addressed responds to the
master by generating an Acknowledge and pulling
SDA low.
A0
0
A1
0
ADDRESS
1001 100
1001 101
1001 110
1001 111
1001 000
1001 001
1001 010
1001 011
0110 111
0
1
1
0
1
1
0
Z
0
Z
1
Z
1
Data transfer is then initiated and sent over eight
clock pulses followed by an Acknowledge bit. During
data transfer SDA must remain stable while SCL is
high, because any change in SDA while SCL is high
is interpreted as a control signal.
Z
Z
Z
Read/Write Operations
Once all data have been transferred, the master
generates a STOP condition. STOP is indicated by
pulling SDA from low to high, while SCL is high.
Accessing a particular register on the TMP435 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte
with the R/W bit low. Every write operation to the
TMP435 requires a value for the Pointer Register
(see Figure 16).
Serial Interface
The TMP435 operates only as a slave device on
either the two-wire bus or the SMBus. Connections to
either bus are made via the open-drain I/O lines, SDA
and SCL. The SDA and SCL pins feature integrated
spike suppression filters and Schmitt triggers to
minimize the effects of input spikes and bus noise.
The TMP435 supports the transmission protocol for
fast (1kHz to 400kHz) and high-speed (1kHz to
3.4MHz) modes. All data bytes are transmitted MSB
first.
When reading from the TMP435, the last value stored
in the Pointer Register by a write operation is used to
determine which register is read by a read operation.
To change the register pointer for a read operation, a
new value must be written to the Pointer Register.
This transaction is accomplished by issuing a slave
address byte with the R/W bit low, followed by the
Pointer Register byte. No additional data are
required. The master can then generate a START
condition and send the slave address byte with the
R/W bit high to initiate the read command. See
Figure 17 for details of this sequence. If repeated
reads from the same register are desired, it is not
necessary to continually send the Pointer Register
bytes, because the TMP435 retains the Pointer
Register value until it is changed by the next write
operation. Note that register bytes are sent MSB first,
followed by the LSB.
Serial Bus Address
To communicate with the TMP435, the master must
first address slave devices via a slave address byte.
The slave address byte consists of seven address
bits, and a direction bit indicating the intent of
executing a read or write operation.
The address of the TMP435 is 4Ch (1001100b).
20
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TMP435
TI [ TEXAS INSTRUMENTS ]
