TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
†
ac timing requirements
‡
’xSN64EPU-12A
’xSN64EPU-12
UNIT
MIN MAX
MIN MAX
t
t
t
t
t
t
t
Access time, CK high to data out, CAS latency = 2 (see Note 8)
Access time, CK high to data out, CAS latency = 3 (see Note 8)
Cycle time, CK, CAS latency = 2
9
10
ns
ns
ns
ns
ns
ns
ns
AC2
AC3
CK2
CK3
LZ
9
9
15
12
3
18
Cycle time, CK, CAS latency = 3
12
Delay time, CK high to DQ in low-impedance state (see Note 9)
Delay time, CK high to DQ in high-impedance state (see Note 10)
Delay time, ACTV command to DEAC or DCAB command
3
10
10
HZ
60 100000
72 100000
RAS
Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR
command
t
t
90
108
30
ns
ns
RC
Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command
(see Note 11)
30
RCD
t
t
t
t
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
Delay time, ACTV command in one bank to ACTV command in the other bank
Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command
30
24
24
36
24
24
ns
ns
ns
ns
RP
RRD
RSA
APR
t
– (CL –1)
t
RP
CK
3
t
t
t
t
t
t
t
t
t
t
Hold time, CK high to data out
3
1
ns
ns
OH
Hold time, address, control, and data input
1.5
10
4
IH
Power down/self-refresh exit time
10
4
ns
CESP
CH
CL
Pulse duration, CK high
ns
Pulse duration, CK low
4
4
ns
Setup time, address, control, and data input
3
3
ns
IS
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command
Delay time, final data in of WRT operation to DEAC or DCAB command
Transition time (see Note 12)
60
15
1
60
20
1
ns
APW
WR
T
ns
5
5
ns
Refresh interval
64
64
ms
REF
n
n
n
n
n
n
Delay time, READ or WRT command to an interrupting command
Delay time, CS low or high to input enabled or inhibited
Delay time, CKE high or low to CK enabled or disabled
Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P
Delay time, ENBL or MASK command to enabled or masked data in
Delay time, ENBL or MASK command to enabled or masked data out
1
0
1
1
0
2
1
0
1
1
0
2
cycle
cycle
cycle
cycle
cycle
cycle
CCD
CDD
CLE
CWL
DID
0
1
0
1
0
2
0
2
DOD
Delay time, DEAC or DCAB command to DQ in high-impedance state,
CAS latency = 2
n
2
2
cycle
HZP2
Delay time, DEAC or DCAB command to DQ in high-impedance state,
CAS latency = 3
n
n
3
0
3
0
cycle
cycle
HZP3
Delay time, WRT command to first data in
0
0
WCD
†
‡
All references are made to the rising transition of CK unless otherwise noted.
-12A speed device is supported only at – 5% to +10% V
DD
isreferencedfromtherisingtransitionofCKthatisprevioustothedata-outcycle.Forexample,thefirstdataoutt
NOTES: 8. t
isreferenced
AC
AC
from the rising transition of CK that is CAS latency – one cycle after the READ command. Access time is measured at output
reference level 1.4 V.
9.
10.
t
is measured from the rising transition of CK that is CAS latency – one cycle after the READ command.
MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
LZ
t
HZ
11. For read or write operations with automatic deactivate, t
12. Transition time, t , is measured between V and V
IH
must be set to satisfy minimum t .
RAS
RCD
.
IL
T
9
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