TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM4SN64EPU (Continued)
TM4SN64EPU-12A
ITEM DATA
= 30 ns
TM4SN64EPU-12
ITEM DATA
= 36 ns
BYTE
NO.
DESCRIPTION OF FUNCTION
Minimum row precharge time
27
28
t
1Eh
18h
1Eh
3Ch
04h
t
24h
18h
1Eh
48h
04h
RP
RP
Minimum row-active to row-active delay
Minimum RAS-to-CAS delay
t
t
= 24 ns
= 30 ns
= 60 ns
t
t
= 24 ns
= 30 ns
= 72 ns
RRD
RCD
RRD
RCD
29
30
Minimum RAS pulse width
t
t
RAS
RAS
31
Density of each bank on module
Superset features (may be used in the future)
SPD revision
16M Bytes
16M Bytes
32–61
62
Rev. 1
8
01h
08h
Rev. 1
90
01h
5Ah
63
Checksum for byte 0–62
64–71
72
Manufacturer’s JEDEC ID code per JEP–106E
97h
9700...00h
97h
9700...00h
†
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
73–90
91
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer specific data
†
126–127 Vendor specific data
‡
128–166 System integrator’s specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
13
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