TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM2SN64EPU (Continued)
TM2SN64EPU-12A
TM2SN64EPU-12
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
V
tolerance =
V
tolerance =
(+10%),
DD
DD
(+10%)/(–5%).
Burst read/write,
precharge all,
Burst read/write,
precharge all,
22
SDRAM device attributes: general
1Eh
0Eh
auto precharge
auto precharge
23
24
Minimum clock cycle time at CL = X – 1
Maximum data-access time from clock at CL = X – 1
Minimum clock cycle time at CL = X – 2
Maximum data-access time from clock at CL = X – 2
Minimum row precharge time
t
= 15 ns
= 9 ns
F0h
90h
00h
00h
1Eh
18h
1Eh
3Ch
04h
t
t
= 18 ns
= 10 ns
N/A
30h
A0h
00h
00h
24h
18h
1Eh
48h
04h
CK
CK
t
AC
AC
25
N/A
26
N/A
N/A
27
t
= 30 ns
t
= 36 ns
RP
RP
28
Minimum row-active to row-active delay
Minimum RAS-to-CAS delay
t
t
= 24 ns
= 30 ns
= 60 ns
t
t
= 24 ns
= 30 ns
= 72 ns
RRD
RRD
29
RCD
RCD
30
Minimum RAS pulse width
t
t
RAS
RAS
31
Density of each bank on module
16M Bytes
16M Bytes
32–61
62
Superset features (may be used in the future)
SPD revision
Rev. 1
7
01h
07h
Rev. 1
89
01h
59h
63
Checksum for byte 0–62
64–71
72
Manufacturer’s JEDEC ID code per JEP–106E
97h
9700...00h
97h
9700...00h
†
Manufacturing location
Manufacturer’s part number
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
73–90
91
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer specific data
†
126–127 Vendor specific data
128–166 System integrator’s specific data
Open
‡
167–255
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
