TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
Tables in this section list the SPD contents as follows:
Table 1–TM2SN64EPU
Table 2–TM4SN64EPU
Table 1. Serial Presence-Detect Data for the TM2SN64EPU
TM2SN64EPU-12A
TM2SN64EPU-12
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
Defines number of bytes written into serial memory
during module manufacturing
0
128 bytes
80h
128 bytes
80h
1
2
3
4
5
6
7
8
Total number of bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM, . . .)
Number of row addresses on this assembly
Number of column addresses on this assembly
Number of module banks on this assembly
Data width of this assembly
256 bytes
SDRAM
11
08h
04h
0Bh
09h
01h
40h
00h
01h
256 bytes
SDRAM
11
08h
04h
0Bh
09h
01h
40h
00h
01h
9
9
1 bank
64 bits
1 bank
64 bits
Data width continuation
Voltage interface standard of this assembly
LVTTL
LVTTL
SDRAM cycle time at maximum supported CAS latency
(CL), CL = X
9
t
= 12 ns
= 9 ns
C0h
90h
00h
t
= 12 ns
= 9 ns
C0h
90h
00h
CK
CK
10
11
SDRAM access from clock at CL = X
t
t
AC
AC
DIMM configuration type (non-parity, parity, error
correcting code [ECC])
Non-Parity
Non-Parity
15.6 µs/
self-refresh
15.6 µs/
self-refresh
12
Refresh rate/type
80h
80h
13
14
SDRAM width, primary DRAM
x8
08h
00h
x8
08h
00h
Error-checking SDRAM data width
N/A
N/A
Minimum clock delay, back-to-back random column
addresses
15
1 CK cycle
01h
1 CK cycle
01h
16
17
18
19
20
Burst lengths supported
Number of banks on each SDRAM device
CAS latencies supported
CS latency
1, 2, 4, 8
0Fh
02h
06h
01h
01h
1, 2, 4, 8
0Fh
02h
06h
01h
01h
2 banks
2 banks
2, 3
0
2, 3
0
Write latency
0
0
Non-buffered/
Non-registered
Non-buffered/
Non-registered
21
SDRAM module attributes
00h
00h
10
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