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TLK10002 参数 Datasheet PDF下载

TLK10002图片预览
型号: TLK10002
PDF下载: 下载PDF文件 查看货源
内容描述: 10Gbps的双通道多速率收发器 [10Gbps Dual-Channel Multi-Rate Transceiver]
分类和应用:
文件页数/大小: 73 页 / 619 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TLK10002  
www.ti.com  
SLLSE75 MAY 2011  
Deep Local Loopback  
The deep local loopback mode is as shown in Figure 14 for Channel A. The configuration is the same for  
Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode,  
the data is accepted on the low speed side SERDES pins (INA*P/N or INB*P/N), traverses the entire transmit  
data path excluding the CML driver, returned through the entire receive data path and sent out through the low  
speed side SERDES pins (OUTA*P/N or OUTB*P/N). The TLK10002 device needs some time for lane alignment  
before passing traffic. The high speed side outputs on HSTXAP/N or HSTXBP/N pins are available for  
monitoring.  
10  
16  
16  
32  
INA0P/N  
LS PRBS  
Verifier  
TX FIFO  
10  
HSTXAP /N  
20  
20  
HS PRBS  
Generator  
16  
INA1P/N  
INA2P/N  
1
0
Pattern  
Generator  
10  
INA3P/N  
High  
Speed  
Side  
Low  
Speed  
Side  
10  
16  
OUTA0P/N  
OUTA1P/N  
32  
SERDES  
SERDES  
RX FIFO  
10  
10  
OUTA2P/N  
OUTA3P/N  
HS PRBS  
Verifier  
LS PRBS  
Generator  
10  
HSRXAP /N  
Pattern  
Verifier  
Figure 14. Deep Local Loopback  
Shallow Local Loopback  
The shallow local loopback mode is as shown in Figure 15 for Channel A. The configuration is the same for  
Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode,  
the data is accepted on the low speed side SERDES pins (INA*P/N or INB*P/N), traverses the entire transmit  
data path excluding the high speed side SERDES, returned through the entire receive data path and sent out  
through the low speed side SERDES pins (OUTA*P/N or OUTB*P/N). The TLK10002 device needs some time  
for lane alignment before passing traffic. The high speed side outputs on HSTXAP/N or HSTXBP/N pins are  
available for monitoring.  
10  
16  
16  
32  
INA0P/N  
LS PRBS  
Verifier  
TX FIFO  
10  
HSTXAP /N  
20  
20  
HS PRBS  
Generator  
16  
INA1P/N  
INA2P/N  
1
0
Pattern  
Generator  
10  
INA3P/N  
High  
Speed  
Side  
Low  
Speed  
Side  
10  
16  
OUTA0P/N  
OUTA1P/N  
32  
SERDES  
SERDES  
RX FIFO  
10  
10  
OUTA2P/N  
OUTA3P/N  
HS PRBS  
Verifier  
LS PRBS  
Generator  
10  
HSRXAP /N  
Pattern  
Verifier  
Figure 15. Shallow Local Loopback  
Copyright © 2011, Texas Instruments Incorporated  
21  
 
 
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