TLK10002
SLLSE75 –MAY 2011
www.ti.com
10
10
16
16
3 2
INA0P/N
TX FIFO
LS PRBS
Verifier
20
HSTXAP/N
16
HS PRBS
Generator
INA1P/N
INA2P/N
1
0
Pattern
Generator
10
INA3P/N
High
Speed
Side
Low
Speed
Side
10
16
20
32
OUTA0P/N
OUTA1P/N
SERDES
SERDES
RX FIFO
10
10
OUTA2P/N
OUTA3P/N
HS PRBS
Verifier
LS PRBS
Generator
10
/N
HSRXAP
Pattern
Verifier
Figure 12. Deep Remote Loopback
Shallow Remote Loopback and Serial Retime
The shallow remote loopback is as shown in Figure 13 for Channel A. The configuration is the same for Channel
B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is
accepted on the high speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the receive data
path and looped back before the low speed SERDES, returned through the transmit data path and sent out
through the high speed side transmit SERDES pins (HSTXAP/N or HSTXBP/N).
The low speed side transmit path SERDES can be optionally enabled or disabled but the PLL needs to be
enabled to provide the required clock.
The low speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. The OUTA*P/N
and OUTB*P/N pins must be correctly terminated. The TLK10002 device needs some time for lane alignment
before passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local
LS_OK_OUT_A/B.
This loopback mode can be used for high speed serial retime operation.
10
16
16
32
INA0P/N
LS PRBS
Verifier
TX FIFO
10
HSTXAP /N
20
20
HS PRBS
Generator
16
INA1P/N
INA2P/N
1
0
Pattern
Generator
10
INA3P/N
High
Speed
Side
Low
Speed
Side
10
16
OUTA0P/N
OUTA1P/N
32
SERDES
SERDES
RX FIFO
10
10
OUTA2P/N
OUTA3P/N
HS PRBS
Verifier
LS PRBS
Generator
10
HSRXAP /N
Pattern
Verifier
Figure 13. Shallow Remote Loopback
20
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