TLK10002
SLLSE75 –MAY 2011
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Line Rate, SERDES PLL Settings, and Reference Clock Selection
The TLK10002 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low
speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers are available
for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies
for various applications.
The external differential reference clock has a large operating frequency range allowing support for many
different applications. The reference clock frequency must be within 200 PPM of the incoming serial data rate
(±100 PPM of nominal data rate), and have less than 40ps of jitter. The following table shows a summary of line
rates and reference clock frequencies used for CPRI/OBSAI for the 1:1, 2:1, and 4:1 operation modes.
Table 3. Specific Line Rate Selection for the 1:1 Operation Mode
LOW SPEED SIDE
HIGH SPEED SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
REFCLKP/N
(MHz)
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
REFCLKP/N
(MHz)
RATE
RATE
4915.2
3840
20
12.5
10
Full
Full
Full
Full
Half
Half
Half
122.88
153.6
4915.2
3840
20
12.5
10
Half
Half
122.88
153.6
3072
153.6
3072
Half
153.6
2457.6
1920
8/10
12.5
10
153.6/122.88
153.6
2457.6
1920
16/20
12.5
10
Quarter
Quarter
Quarter
Eighth
153.6/122.88
153.6
1536
153.6
1536
153.6
1228.8
8/10
153.6/122.88
1228.8
16/20
153.6/122.88
Table 4. Specific Line Rate Selection for the 2:1 Operation Mode
LOW SPEED SIDE
HIGH SPEED SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
REFCLKP/N
(MHz)
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
REFCLKP/N
(MHz)
RATE
RATE
4915.2
3840
20
12.5
10
Full
Full
122.88
153.6
9830.4
7680
20
Full
Full
122.88
153.6
12.5
3072
Full
153.6
6144
10
Full
153.6
2457.6
1920
8/10
12.5
10
Full
153.6/122.88
153.6
4915.2
3840
16/20
12.5
Half
153.6/122.88
153.6
Half
Half
1536
Half
153.6
3072
10
Half
153.6
1228.8
768
8/10
10
Half
153.6/122.88
153.6
2457.6
1536
16/20
10
Quarter
Quarter
Eighth
153.6/122.88
153.6
Quarter
Quarter
614.4
8/10
153.6/122.88
1228.8
16/20
153.6/122.88
Table 5. Specific Line Rate Selection for the 4:1 Operation Mode
LOW SPEED SIDE
HIGH SPEED SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
REFCLKP/N
(MHz)
LINE RATE
(Mbps)
SERDES PLL
REFCLKP/N
(MHz)
RATE
RATE
MULTIPLIER
16/20
10
2457.6
1536
8/10
10
Full
Half
153.6/122.88
153.6
9830.4
6144
Full
Full
153.6/122.88
153.6
1228.8
768
8/10
10
Half
153.6/122.88
153.6
4915.2
3072
16/20
10
Half
153.6/122.88
153.6
Quarter
Quarter
Half
614.4
8/10
153.6/122.88
2457.6
16/20
Quarter
153.6/122.88
The above tables indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6MHz and
122.88MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has
been given for each reference clock frequency respectively. For each channel, the low speed side and the high
speed side SERDES use the same reference clock frequency. Note that Channel A and B are independent and
their application rates and references clocks are separate.
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