ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
serial-port timing parameters (see Figure 23 and Figure 24)
320C30-40
320C30-50
CLOCK
SOURCE
NO.
UNIT
MIN
MAX
MIN
MAX
Delay time, H1 high to
internal CLKX/R
65
t
t
13
10
ns
d(H1-SCK)
CLKX/R ext
t
× 2.5*
t
× 2.6*
Cycle time,
CLKX/R
c(H)
c(H)
66
67
ns
ns
c(SCK)
32
× 2
32
× 2 *
CLKX/R int
CLKX/R ext
t
× 2
t
*
t
× 2
t
c(H)
c(H)
c(H)
c(H)
Pulse
t
+12*
t
+10*
c(H)
c(H)
duration,
CLKX /R
high/low
t
w(SCK)
CLKX/R int
[t
/2]−15
[t
/ 2]+5
[t
/2]−5
[t
/ 2]+5
c(SCK)
c(SCK)
c(SCK)
c(SCK)
68
69
t
t
Rise time, CLKX/R
Fall time, CLKX/R
7*
7*
6*
6*
ns
ns
r(SCK)
f(SCK)
Delay time,
CLKX to DX
valid
CLKX ext
CLKX int
CLKR ext
CLKR int
CLKR ext
CLKR int
30
17
24
16
70
71
72
t
ns
ns
ns
d(DX)
Setup time,
DR before
CLKR low
9
21
9
9
17
7
t
t
su(DR)
Hold time,
DR from
CLKR low
h(DR)
0
0
Delay time,
CLKX to
internal FSX
high/low
CLKX ext
CLKX int
27
15
22
15
73
74
75
t
t
t
ns
ns
ns
d(FSX)
su(FSR)
h(FS)
Setup time,
FSR before
CLKR low
CLKR ext
CLKR int
9
9
7
7
Hold time,
FSX/R input
from
CLKX/R ext
CLKX/R int
CLKX ext
9
0
7
0
CLKX/R low
Setup time,
external FSX
before CLKX
high
−[t
c(H)
− 8]
[t
/ 2]−10*
−[t
c(H)
− 8]
[t
/ 2]−10*
c(SCK)
c(SCK)
76
77
t
ns
ns
su(FSX)
CLKX int
−[t
c(H)
−21]
t
/2*
−[t
c(H)
−21]
t
/2*
c(SCK)
30
c(SCK)
Delay time,
CLKX to first
DX bit, FSX
precedes
CLKX ext
CLKX int
24
t
d(CH-DX)V
18
30
14
24
CLKX high
Delay time, FSX to first DX
bit, CLKX precedes FSX
78
79
t
t
ns
ns
d(FSX-DX)V
Delay time, CLKX high to DX
high impedance following last
data bit
17*
14*
dDXZ
* This parameter is not production tested.
32
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