ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
reset timing (continued)
CLKIN
50
RESET
51
53
52
H1
54
H3
Ten H1 Clock Cycles
56
(X)D
(see Note A)
57
58
55
(X)A
(see Note B)
Control Signals
(see Note C)
59
IACK
60
Asynchronous
Reset Signals
(see Note D)
NOTES: A. In this diagram X(D) includes D31−D0 and XD31−XD0.
B. In this diagram, (X)A includes A23−A0 and XA12−XA0.
C. Control signals include STRB, MSTRB, and IOSTRB.
D. Asynchronous reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1,
TCLK0, and TCLK1.
E. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In micromputer mode, the reset
vector is fetched twice, with no software wait states.
Figure 20. Timing for Reset [P=t
]
c(Cl)
29
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