ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay of one clock cycle can
occur. R/W and XR/W are in the high-impedance state during reset and can be provided with a resistive pullup,
nominally 18 kΩ to 22 kΩ, to prevent spurious writes from occurring. The asynchronous reset signals include
XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. HOLD is an asynchronous input and
can be asserted during reset.
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states
and, therefore, results in slow external accesses until these registers are initialized.
timing parameters for RESET [P = t
] (see Figure 9 and Figure 20)
c(CI)
320C30-40
320C30-50
NO.
UNIT
MIN
10
2
MAX
P*
MIN
10
2
MAX
50
51
52
t
t
t
Setup time, RESET before CLKIN low
P*
10
10
ns
ns
ns
su(RESET)
†
Delay time, CLKIN high to H1 high
14
d(CLKINH-H1H)
d(CLKINH-H1L)
†
Delay time, CLKIN high to H1 low
2
14
2
Setup time, RESET high beforeH1 low after ten H1 clock
cycles
53
t
9
7
ns
su(RESETH-H1L)
†
54
55
56
57
58
59
t
t
t
t
t
t
Delay time, CLKIN high to H3 low
2
2
14
14
15*
9*
2
2
10
10
12*
8*
ns
ns
ns
ns
ns
ns
d(CLKINH-H3L)
d(CLKINH-H3H)
dis(H1H-XD)
†
Delay time, CLKIN high to H3 high
Disable time, H1 high to (X)D high-impedance state
Disable time, H3 high to (X)A high-impedance state
Delay time, H3 high to control signals high
Delay time, H1 high to IACK high
dis(H3H-XA)
9*
8*
d(H3H-CONTROLH)
d(H1H-IACKH)
9*
8*
Disable time, RESET low to asynchronous reset signals in
the high-impedance state
60
t
21*
17*
ns
dis(RESETL-ASYNCH)
†
See Figure 9 for temperature dependence for the 40-MHz SMJ320C30.
* This parameter is not production tested.
28
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