ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal.
timing parameters for IACK (see Figure 22)
320C30-40
MIN MAX
320C30-50
MIN MAX
†
NO.
UNIT
63
64
t
t
Delay time, H1 high to IACK low
Delay time, H1 high to IACK high
9
9
7
7
ns
ns
d(H1H-IACKL)
d(H1H-IACKH)
†
Numbers in this column match those used in Figure 22.
Fetch IACK
Instruction
IACK
Data Read
H3
H1
63
64
IACK
Address
Data
Figure 22. Timing for Interrupt-Acknowledge (IACK)
31
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