ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 25 occurs; otherwise, an additional delay of one clock cycle is
possible.
The “timing parameters for HOLD/HOLDA” table defines the timing parameters for the HOLD and HOLDA
signals.
The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, allowing
the processor to continue until a second write is encountered.
HOLD/HOLDA timing (see Figure 25)
320C30-40
320C30-50
†
NO.
UNIT
MIN
13
MAX
MIN
10
MAX
80
81
82
83
84
85
86
87
88
89
90
91
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, HOLD before H1 low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(HOLD)
v(HOLDA)
w(HOLD)
Valid time, HOLDA after H1 low
0*
9
0*
7
Pulse duration, HOLD low
2t
c(H)
2t
c(H)
Pulse duration, HOLDA low
t
−5*
t
−5*
w(HOLDA)
d(H1L-SH)H
dis(H1L-S)
en(H1L-S)
dis(H1L-RW)
en(H1L-RW)
dis(H1L-A)
en(H1L-A)
dis(H1H-D)
c(H)
c(H)
7
Delay time, H1 low to STRB high for a HOLD
Disable time, H1 low to STRB high impedance
Enable time, H1 low to STRB active
Disable time, H1 low to R/W high impedance
Enable time, H1 low to R/W active
Disable time, H1 low to address high impedance
Enable time, H1 low to address valid
Disable time, H1 high to data high impedance
0*
9*
9*
0*
*
*
*
*
*
*
8
7
8
7
8
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
9*
9*
9*
9*
13*
12*
12*
8
*
†
Numbers in this column are used in Figure 25.
* This parameter is not production tested.
34
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