ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
general-purpose I/O timing
Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The contents of the
internal-control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The following table defines peripheral pin general-purpose I/O timing parameters.
timing parameters for peripheral pin general-purpose I/O (see Note 11 and Figure 26)
320C30-40
320C30-50
†
NO.
UNIT
MIN
10*
0*
MAX
MIN
9*
MAX
92
93
94
t
t
t
Setup time, general-purpose input before H1 low
Hold time, general-purpose input after H1 low
Delay time, general-purpose output after H1 high
ns
ns
ns
su(GPIOH1L)
h(GPIOH1L)
d(GPIOH1H)
0*
13*
10*
†
Numbers in this column are used in Figure 26.
* This parameter is not production tested.
NOTE 11: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined
by the contents of internal control registers associated with each peripheral.
H3
H1
94
93
94
92
Peripheral
Pin
Figure 26. Timing for Peripheral Pin General-Purpose I/O
36
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